1. Technical Field
The disclosure relates generally to integrated circuit (IC) chip fabrication, and more particularly, to inductors for use in IC chips and related methods.
2. Background Art
An inductor is a passive electrical structure used in electrical circuits for its property of inductance. An inductor can take many forms. Building high-quality on-chip inductors has attracted tremendous interest for radio frequency integrated circuit (RFIC) design and integrated circuit (IC) chip manufacturers. In particular, high-quality on-chip inductors have been widely demonstrated as a key factor for successfully integrating RF building blocks. As shown in FIG. 1, inductors currently require wide metal lines (e.g., 15-20 μm) and a large number of turns with narrow spacing to provide a competitive quality factor (Q factor). Q factor of an inductor is equal to the ratio of an inductive reactance (stored energy) thereof to a resistance (loss) thereof at a given frequency, and is an indication of an inductor's efficiency. Generally, as line width increases, line impedance decreases—increasing the Q factor.
There are several disadvantages associated with the current industry standard layout which uses wide solid metal lines. First, as the width of lines used increases, the Q factor increase is limited due to an increase in substrate capacitance at high frequency, which also causes a reduced self-resonance frequency. Second, Eddy current effects increase as metal line widths increase, particularly for multiple turn inductors with many adjacent metal traces. Eddy current refers to the electrical situation in which a changing magnetic field intersects a conductor creating a circulating flow of electrons within the conductor, which generates electromagnetic fields that oppose an applied magnetic field. Eddy currents increase resistance at RF frequencies, further reducing the inductor Q factor.
Third, the conventional manufacturing of inductors from copper (Cu) is very difficult due to manufacturing process sensitivities associated with high local pattern densities, i.e., a large amount of metal structures within a given area. For example, chemical mechanical polish (CMP) is prone to over-polish high pattern density regions, which can impact the sheet resistance significantly. Severe over-polish can also result in subsequent level shorting, as topography degradation replicates through downstream levels and processing. Manufacturing is particularly sensitive to regions of high stacked metal density, which is common in multi-level spiral inductors. The standard method of placing blanket holes (or cheesing) the metal structures randomly to reduce pattern density after layout submission for manufacturing is not optimal for inductors because the sheet resistance increases, thereby negatively impacting the Q factor. The random cheesing of inductors also introduces compact model inaccuracy and asymmetry in geometries where symmetry may be critical.